During past few years FPGAs have seen a rapid growth in their logic capacity which has led to the increasing use of FPGAs for the implementation of arithmetic-intensive applications. Arithmetic-intensive applications often contain large portion of datapath circuits. Datapath circuits usually contain hard-blocks (e.g. multipliers, adders, memories etc) that are connected together by regularly structured signals called buses. Conventional FPGAs do not use the regularity of datapath circuits. So it is possible to modify the conventional FPGA architectures to exploit the regularity of datapath circuits and achieve significant area savings. This paper describes a new tree-based FPGA architecture that uses bus-based connections and exploits the regularity of datapath circuits to achieve area savings. Experiments show that the proposed architecture is 24%, 21% more area efficient than conventional mesh-based and tree-based architectures respectively.