Analog design automation has been considered as a holy grail for the last few decades. In this tutorial, the presenters focus on THREE main related aspects: Modeling for structured analog design, hierarchical analog IP synthesis and layout-aware synthesis. To solve the problem of analog IP synthesis, historically, two research directions have emerged: knowledge-based procedural approach based on inversion factor and simulation-based. Traditionally, the knowledge-based procedural approach, based on retargeting aspects of known topology, was appreciated for its high-speed interactivity but suffered from inaccuracy and the long time and effort necessary to add a new topology. The simulation-based approach was appreciated for its generality but suffered from large execution time, hence, lost the advantage of interactivity. In this tutorial, the complete history and the emerging directions of analog design automation shall be presented. Part (I) illustrates the state-of-the-art knowledge–based synthesis system called PAD (Procedural Analog Design), which is developed at the EPFL in Lausanne, Suisse. Many key concepts in PAD are highlighted such as the inversion factor approach for device modeling and its application to the automation of analog structures (gain cells, biasing, references). Then an extension of this approach toward the operational transconductance amplifiers, OpAmp, comparator topologies including robust biasing techniques will be shown. This first part is mainly dedicated to review the techniques of the procedural structured approach that make the retargeting aspect of analog circuits feasible and will depict the limitation of this aspect. Part (II) analyses the main characteristics of knowledge-based synthesis systems. Consequently, a new class of synthesis systems known as knowledge-aware systems shall be introduced. We show the capacity of such systems to hierarchically size and bias an analog IP. This is accomplished by automatically generating reusable and consistent sizing procedures for the analog IP that respects topology structure, designer’s hypotheses and design constraints. These sizing procedures are guaranteed by construction to be technology independent and produce simulator-like quality designs interactively. The application of these systems for analog IP synthesis and technology migration shall be presented. We also show how these systems handle efficiently deep submicron problems such stress effects and well-proximity effects. As a case study, we present the project CHAMS (successor of the project CAIRO+), developed at LIP6 laboratory in Paris, France. Part (III) shows how knowledge-aware synthesis systems can be coupled with automatic layout generation tools to deliver the final layout of the analog IP. Therefore, the so-called layout-aware synthesis flow is presented. In this approach, both sizing and layout generation are merged into a single, automated, optimization-based process. The main goal is to completely remove from the flow the time-consuming iterations between sizing and layout that are typically necessary to deal with layout parasitics and with geometry/area optimization (two aspects that are tightly coupled). With the layout-aware flow, the final solution is, at the same time, both robust against parasitics and fully optimized with respect to geometry (e.g., occupied area, aspect ratio). Moreover, the layoutaware technique is able to provide trade-offs hyper-curves (also known as Pareto fronts) that reveal bi-univocal relationships between design variables (e.g., device dimensions and biasing), best achievable performances (e.g., gain and speed) and layout (parasitics and geometry).