A novel hardware architecture for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper, aiming to reduce the computation complexity coming with this module and to accelerate the concerned calculations. We propose a new pipelined structure that we named Processing Element (PE) to execute all angular modes, and we repeat it in five paths which compose our architecture. We propose also another structure perform the Planar mode. This architecture supports all intra prediction modes for all block sizes. The synthesis results show that our solution can run at 213 MHz for FPGA Xilinx Virtex 6 and is capable to process real time 120 1080p FPS or 30 4K FPS.