The goal of this paper is to provide design considerations for the use of low gain amplifier presents in the Multiplying Analog-to-Digital Converter (MDAC) of pipelined ADCs with gain error correction in the digital domain. Using low gain amplifier in the MDAC makes the pipelined ADC more susceptible to gain variation and harmonic distortion, impacting the ADC performance. Theory and simulations are presented to provide design insight into the trade-off between minimum gain and its variations to preserve the calibrated ADC performance. These considerations are demonstrated on the MDAC of a 12 bit digitally calibrated pipelined ADC designed in 40nm CMOS technology.