Reliability of Sigma-Delta modulator
Fiabilisation de convertisseurs analogique-num´erique versatiles `a modulation SD
Résumé
With the continuous scaling down of CMOS technology, reliability problems such as ageing effect induced
parameter degradations and process variation become critical aspects and major bottleneck in integrated circuits
(ICs) design. Their joint effects impact the ICs performance and service lifetime. Traditionally, according to
specifications, ICs are often designed conservatively to ensure fabricated systems can meet reliability goals,
which leads to a reduced performance. New design-for-reliability (DFR) loop and variability-aware methodologies
need to be developed for sub-micron technology. Analog-to-digital sigma-delta modulators (SDMs) is the
object of study in this thesis. Physical mechanisms of time dependent ageing degradation (NBTI, HCI, TDDB)
and process variation are investigated. Reliability analysis on SDMs is performed with 65 nanometer CMOS
technology. Information such as system lifetime, sensitive blocks and weak spots must be evaluated. Statistical
analysis for process variations is implemented by using DoE-RSM method. Design methodologies using behavioral
modeling, nominal simulation, hierarchy circuit design and quadratic response surface modeling applied to
analog/mixed integrated circuit is proposed and validated.
Origine : Fichiers produits par l'(les) auteur(s)
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