A heterogeneous Application Specific FPGA (ASIF) is a modified form of heterogeneous FPGA which is designed to explore the solution space between FPGAs and ASICs. Compared to an equivalent FPGA architecture, it has reduced flexibility but improved density. On the other hand, compared to an ASIC, it has reconfigurability but increased area. This work presents a new heterogeneous tree-based ASIF. Four ASIF generation techniques are explored for it using 17 benchmarks. Experimental results show that, on average, the best ASIF generation technique gives 70% area gain when compared to an equivalent FPGA architecture. Further experiments are performed to determine the effect of Lookup-Table (LUT) and arity size on heterogeneous tree-based ASIF. Later, area comparison between tree-based ASIF and equivalent mesh-based ASIF shows that the former gives either equal or better results than the latter. Finally quality comparison of two ASIFs shows that, on average, tree-based ASIF produces 18% better area results than mesh-based ASIF.