Sine-shaped feedback DAC was proposed to be used in continuous-time ΣΔ ADCs for its immunity to clock jitter. However, in a sine-shaped DAC, the carrier is used as an analog signal to mix with the data, consequently, all the carrier noise appears in the sine-shaped data. The effect of carrier noise was studied before, but the analysis was based on the assumption of white noise, which is not true in real PLLs. In this work, we present a simple, intuitive, and accurate model that can predict the effect of the clock noise on the sine-shaped DAC. The model is generic and can be applied for any noise profile. We tried to keep it as close as possible to the noise profile of a real clock source. The analysis is verified by simulation and measurement results.