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Communication Dans Un Congrès Année : 2015

HLS based design of a mixed architecture for H.264/AVC CAVLD

Résumé

Mixed Hardware/Software architectures are often attractive solutions for Embedded System especially for real time applications. However, when the complexity of hardware functions grows, hand coding at Register-Transfer Level (RTL), which is already low and error prone, adds debugging and verification overheads that impact severely the time and costs of development. Therefore, High Level Synthesis (HLS) brings a solution to decrease the design time of dedicated hardware and keep the high abstraction level of software development. In this context we propose a HLS based design flow for Hardware/Software architecture on top of Catapult C Synthesis. We illustrate the effectiveness of this approach on the practical implementation example of a full H264/AVC video compression decoder. The hardware accelerator is the CAVLD module that takes 14% from the decoder execution time. Three architectures are presented for this module. The best one offers 85% of gain compared to software execution. The proposed architectures are implemented on a Xilinx FPGA-embedded systems prototyping board considering the PowerPC processor and a PLB bus for data communications with the CAVLC accelerator.
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Dates et versions

hal-01192789 , version 1 (03-09-2015)

Identifiants

Citer

Taheni Dammak, Sébastien Bilavarn, Nouri Masmoudi. HLS based design of a mixed architecture for H.264/AVC CAVLD. 12th International Multi-Conference on Systems, Signals and Devices Program, SSD 2015, Mar 2015, Mahdia, Tunisia. pp.1-4, ⟨10.1109/SSD.2015.7348095⟩. ⟨hal-01192789⟩
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