HLS based design of a mixed architecture for H.264/AVC CAVLD
Résumé
Mixed Hardware/Software architectures are often attractive solutions for Embedded System especially for real time applications. However, when the complexity of hardware functions grows, hand coding at Register-Transfer Level (RTL), which is already low and error prone, adds debugging and verification overheads that impact severely the time and costs of development. Therefore, High Level Synthesis (HLS) brings a solution to decrease the design time of dedicated hardware and keep the high abstraction level of software development. In this context we propose a HLS based design flow for Hardware/Software architecture on top of Catapult C Synthesis. We illustrate the effectiveness of this approach on the practical implementation example of a full H264/AVC video compression decoder. The hardware accelerator is the CAVLD module that takes 14% from the decoder execution time. Three architectures are presented for this module. The best one offers 85% of gain compared to software execution. The proposed architectures are implemented on a Xilinx FPGA-embedded systems prototyping board considering the PowerPC processor and a PLB bus for data communications with the CAVLC accelerator.
Mots clés
video coding
variable length codes
high level synthesis
data compression
embedded systems
adaptive decoding
adaptive codes
HLS based design flow
mixed hardware-software architectures
Catapult C Synthesis
H264/AVC video compression decoder
hardware accelerator
decoder execution time
Xilinx FPGA-embedded systems
PowerPC processor
PLB bus
data communications
CAVLC accelerator
context adaptive variable length decoding
Computer architecture
Decoding
Hardware
Software
Encoding
Field programmable gate arrays
Graphics