Surface effects on split C-V measurements on SOI wafers
Résumé
The experimental conditions for split C-V technique in pseudo-MOSFET configuration are investigated. Previous studies showed that the capacitance variation with frequency is dominated by the equivalent RC circuit describing the channel formation. Therefore, an extrapolation of interface trap density was not possible. Here, we demonstrate that the conductance term, measured at low frequency as a function of gate bias, is clearly influenced by the quality of the top wafer surface, potentially leading to the evaluation of interface traps.