Large variety of channel coding techniques are specified in existing and emerging digital communication standards, each suitable for specific application needs (frame size, transmission channel, signal-to-noise ratio, bandwidth, etc.). Considering the emerging multi-mode and multi-standard applications, as well as the increasing interest for Software Defined Radio and Cognitive Radio applications, flexible implementations combining multiple error correction techniques become mandatory. However, the need of optimal solutions in terms of performance, area, and power consumption is increasing too and cannot be neglected against flexibility. Towards fulfilling this emerging requirement, recent efforts have targeted the use of Application-Specific Instruction-set Processor (ASIP) models. Such an architecture model enables the designer to freely tune the flexibility/performance trade-off as required by the considered application. In this context, the present chapter illustrates the benefits of the ASIP design approach for multi-standard channel decoders. By considering mainly the challenging turbo codes decoding and the diverse related parameters and requirements, a complete design flow is illustrated. The chapter presents in addition the trend towards the use of ASIP design approach in the context of the increased flexibility requirement to support multiple types of channel codes. Furthermore, different architecture alternatives and design objectives are explored and illustrated. In order to be relevant to existing and emerging standards, the flexibility support is limited to the codes parameters specified in WiFi, WiMAX, and LTE. This also enables to review and compare recent existing state-of-the-art implementations. The presented results demonstrate the rapid design cycle and the effectiveness offered by the ASIP-based design approach in this application domain to fine tune design trade-offs with respect to diverse design objectives.