In order to anticipate the further demands of miniaturization and integration of “System in Package”, the technology of 3D Through-Silicon-Vias (TSVs) has been introduced at NXP Semiconductors. The copper electroplating (ECD), one of the TSVs enabled technologies, has been developed in a pilot line. A continuous and conductive copper seed layer into vias is required for a successful via plating. The microvias, for an aspect-ratio (AR) up to 2.4, were able to be successfully coated either by a sputtered or an electro-grafted copper layer. The latter one exhibits a more uniform aspect which is more convenient for electroplating. Pulsed current was proved to be more adapted to fill the as order as of hundred micrometer deep microvias than the direct current in spite of its longer processing time. Even though, deeper microvias were proved to be more difficult to fill due to the increasing mass transfer constraint inside. Applying a patterned photoresist mask on the field could combine the Back-End-Of-Line (BEOL) passive components formation and the microvia filling in one processing step. However, the thickness of the mask imposed a relatively short microvia filling time. With a well tuned pulsed current, a well adjusted solution composition and an improved cell hydrodynamic environment, the 180 micrometer deep vias can be more than half filled at a “superfilling” manner for 6 hours with a layer slightly growing out of the mask on the field. The “side effect” caused more via filling at the edge than at the center of six-inch wafer, whereas the varying local via density seemed to do not impact the plating performance across the wafer.