This paper presents a so-called "3D power packaging structure", in which silicon-carbide power devices are placed between two ceramic-metal substrates (DBC). This allows for more efficient cooling of the transistors (double side cooling), better electrical performance (lower resistance and inductance), and higher level of integration. The paper presents the manufacturing steps required to produce and assemble the different parts of the module: The substrates are etched with a high-resolution, two step process which exceeds the common design rules. The module is assembled using silver sintering. A new approach is used for the encapsulation of this intricate structure: parylene HT.Some of these results were published in the IMAPS HiTEC conference in may 2014. For this presentation, we will focus on new results: the electrical characterization (static and dynamic) of the power module. A half-bridge module, using two SiC JFET transistors is used for these tests.