Bit Error Rate Performance Evaluation of a Silicon-on-Insulator Optical-Network-on-Chip Router in a WDM configuration
Résumé
We present a Bit Error Rate characterization of a microring-based integrated router in Silicon-on-Insulator technology, suitable for optical networking at chip level. The switching functionalities are evaluated in a single channel (10 Gbit/s) and in a 3-channels (3x10 Gbit/s) WDM configuration. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.