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Communication Dans Un Congrès Année : 2013

Bit Error Rate Performance Evaluation of a Silicon-on-Insulator Optical-Network-on-Chip Router in a WDM configuration

Résumé

We present a Bit Error Rate characterization of a microring-based integrated router in Silicon-on-Insulator technology, suitable for optical networking at chip level. The switching functionalities are evaluated in a single channel (10 Gbit/s) and in a 3-channels (3x10 Gbit/s) WDM configuration. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.

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Dates et versions

hal-01075438 , version 1 (17-10-2014)

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Parini Alberto, Gaetano Bellanca, Andrea Annoni, Francesco Morichetti, Andrea Melloni, et al.. Bit Error Rate Performance Evaluation of a Silicon-on-Insulator Optical-Network-on-Chip Router in a WDM configuration. 39th European Conference on Optical Communication (ECOC 2013), Sep 2013, Londres, United Kingdom. pp.897-899, ⟨10.1049/cp.2013.1572⟩. ⟨hal-01075438⟩
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