A new electro-thermal model of a semiconductor device has been carried-out in order to investigate electrical and thermal mappings of power devices during critical operations. This model allows evaluating the effect of chip metallization ageing on temperature distributions and current sharing between cells within an IGBT chip during short-circuits operations. One of the failure mechanisms in IGBT is due to the switch on of the npnp parasitic thyristor. This phenomenon so called Latch-up and often illustrated as a drastic increasing of the total current in the power IGBT leads in many cases to the destruction of the device. By taking into account, in the model, the parasitic inductance, IGBT dynamic latch-up will be performed and simulation results will be compared to experimental one.