In this paper, a smart adaptive RF power amplifier linearization technique is presented. We invest a Mixed-Signal Cartesian Feedback Loop design to train an embedded Random Access Memory in order to overcome digital-stage latency and bandwidth limitation. The new design consists of a traditional analog stage including filters, I/Q modulator, feedback I/Q demodulator and an improved digital stage which adjusts the phase misalignment around the loop and updates the RAM. We used a not fully-pipelined CORDIC design for the digital part in order to improve the system operating frequency without increasing the silicon surface area. We implemented this design for the UMTS standard using ASIC 65nm low power technology. We reached 230 MHz with system power consumption less than 6 mw which is better than a fully analog system (8.8 mW).