High speed low complexity radix-16 Max-Log-MAP SISO decoder
Résumé
At present, the main challenge for hardware implementation turbo decoders is to achieve the high data rates required by current and future communication system standards. In order to address this challenge, a low complexity radix-16 SISO decoder for the Max-Log- MAP algorithm is proposed in this paper. Based on the elimination of parallel paths in the radix-16 trellis diagram, architectural solutions to reduce the hardware complexity of the different blocks of a SISO decoder are detailed. Moreover, two complementary techniques are introduced order to overcome BER/FER performance degradation when turbo decoders based on the proposed SISO decoder are considered. Thus, a penalty lower than 0.05dB is observed for a 8 state binary turbo code with respect to a traditional radix-2 turbo decoder for 6 decoding iterations.
Mots clés
binary codes
codecs
error statistics
trellis codes
8 state binary turbo code
Decoding
BER/FER performance degradation
Computer architecture
Complexity theory
Bit error rate
turbo decoders
the hardware complexity
radix-2 turbo decoder
radix-16 trellis diagram
decoding iterations
high speed low complexity radix-16 Max-Log-MAP SISO decoder
communication system standards
architectural solutions
Max-LogMAP algorithm
Systematics
Hardware
Measurement
high radix architectures
Turbo codes
Domaines
ElectroniqueOrigine | Fichiers produits par l'(les) auteur(s) |
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