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Article Dans Une Revue Journal of Electronic Testing: : Theory and Applications Année : 2013

On the Simulation of HCI-Induced Variations of IC Timings at High Level

Résumé

Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter HCI. This mechanism causes timing degradation and possibly failures in ICs. The evaluation of timing degradation early in the design flow becomes a must-have to ensure the expected time-to-market and IC lifetime. In this paper, we propose a framework for simulating and analyzing the HCI-induced timing variations at high abstraction level. We first present a bottom-up approach to move information about timing degradation up to the higher abstraction layers. Then, we describe a simulation framework for analyzing the HCI-induced timing variations, and we evaluate its performance and accuracy. Finally, by considering a sample processor, we analyze the impact of the instruction set architecture on slack times and critical paths.

Dates et versions

hal-00950233 , version 1 (21-02-2014)

Identifiants

Citer

Olivier Héron, Clément Bertolini, Nicolas Ventroux, Chiara Sandionigi, François Marc. On the Simulation of HCI-Induced Variations of IC Timings at High Level. Journal of Electronic Testing: : Theory and Applications, 2013, 29, pp.127-141. ⟨10.1007/s10836-013-5368-x⟩. ⟨hal-00950233⟩
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