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Communication Dans Un Congrès Année : 2013

Redundancy Method to assess Electromigration Lifetime in power grid design

Résumé

The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.
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Dates et versions

hal-00915971 , version 1 (12-12-2013)

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Boukary Ouattara, Lise Doyen, David Ney, Habib Mehrez, Pirouz Bazargan-Sabet, et al.. Redundancy Method to assess Electromigration Lifetime in power grid design. IEEE International Interconnect Technology Conference (IITC),, Jun 2013, Kyoto, Japan. pp.81-83, ⟨10.1109/IITC.2013.6615570⟩. ⟨hal-00915971⟩
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