In this paper we propose a flexible and efficient architecture design of an application-specific processor dedicated for MIMO MMSE-IC turbo equalization using the NISC design approach. Hardware resources are shared and reused through all required computations for different system configurations. The performance is enhanced by the direct controlling of hardware resources at each clock cycle. In order to evaluate the efficiency of the investigated architecture model, a fair comparison is conducted with a state-of-the-art ASIP (Application-Specific Instruction-set Processor) that supports same flexibility parameters and uses identical computational resources.