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Article Dans Une Revue Microelectronics Journal Année : 2008

Design of a soft-error robust microprocessor

Résumé

The costs to protect a commercial microprocessor against soft errors are discussed in this work. Based on hardware and time redundancies, a protection scheme was designed at RT level to mitigate transient faults on combinational and memory circuits. A fault-tolerant IC version of a mass-produced 8-bit microprocessor is protected by the scheme. Design issues and results in area, performance and power are presented comparing the robust microprocessor with its non-protected version. The costs by flip-flop are also discussed permitting to estimate the overheads in area for any architecture. Furthermore, the RT-level protection scheme is compared with an electrical-level scheme based on a non-standard gate.

Dates et versions

hal-00873149 , version 1 (15-10-2013)

Identifiants

Citer

Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis. Design of a soft-error robust microprocessor. Microelectronics Journal, 2008, 40 (7), pp.1062-1068. ⟨10.1016/j.mejo.2008.10.001⟩. ⟨hal-00873149⟩

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