Implementation of DPA Attacks on Flash-Based FPGA Hardware AES Cipher and Proposal of a Novel Correlated Power Noise Generator Countermeasures
Résumé
In this paper, authors conducted a successful DPA attack on an AES hardware implementation on Flash-based FPGA technology. Correlation analysis method is used to reduce DPA attack data processing time. An experimental set-up is defined to implement on an FPGA board critical AES modules and DPA attack. As main contribution, this work proved the success of DPA attack on Flash-based FPGA. Experimental results showed that for different secret key values a maximum of correlation with the correct key is obtained during 20 mn of data processing time. To secure the hardware AES cipher against this DPA attack with reduced area and power consumption overhead a novel countermeasure based on a correlated power noise generator is proposed to remove the design power correlation with the secret key. Robustness of proposed countermeasure is proved against DPA attack implementation on Actel Fusion FLASH FPGA. The implementation on Xilinx Virtex 4 of the full 128-bits AES with the CPNG countermeasure leads to a smaller area overhead (12.78 times less) than conventional masking scheme countermeasure.