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Communication Dans Un Congrès Année : 2013

A Low-Power Content-Adressable-Memory Based on Clustered-Sparse-Networks

Résumé

A low-power Content-Addressable-Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The proposed architecture is based on a recently developed clustered-sparse-network using binary-weighted connections that on-average will eliminate most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared to that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. A 0.13 um CMOS technology was used for simulation purposes. The energy consumption and the search delay of the proposed design are 9.5%, and 30.4% of that of the conventional NAND architecture respectively with a 3.4% higher number of transistors.
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Dates et versions

hal-00856950 , version 1 (02-09-2013)

Identifiants

  • HAL Id : hal-00856950 , version 1

Citer

Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross. A Low-Power Content-Adressable-Memory Based on Clustered-Sparse-Networks. ASAP 2013 : 24th IEEE International Conference on Application-specific Systems, Architectures and Processors, Jun 2013, Washington, United States. ⟨hal-00856950⟩
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