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Communication Dans Un Congrès Année : 2012

Through-Silicon-Via Built-In Self-Repair for Aggressive 3D Integration

Résumé

Three-dimensional (3D) integration by die-/wafer-level stacking becomes a reality, as Through-Silicon-Via technologies emerge. However, poor reliability and yield of TSV interconnects remain major challenges of this promising technology. In this paper, we propose an efficient Built-In Self-Repair (TSV-BISR) strategy for TSV faults due to manufacturing and aging defects. After interconnect tests, we replace faulty TSVs with fault-free spares using shift operations. Among the benefits of this solution is that the self-repair signals are determined on-chip without any external intervention. Moreover, we show that with TSV-BISR better reparability is achieved with fewer spares than in existing TSV repair techniques. We also show that for 3D chips with interconnect reparability targets above 98% we reduce the area needed for spares and repair logic by up to 40%.
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Dates et versions

hal-00841561 , version 1 (05-07-2013)

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Citer

M. Nicolaidis, V. Pasca, Lorena Anghel. Through-Silicon-Via Built-In Self-Repair for Aggressive 3D Integration. IEEE 18th International On-Line Testing Symposium (IOLTS), Jun 2012, Sitges, Spain. pp.91-96, ⟨10.1109/IOLTS.2012.6313847⟩. ⟨hal-00841561⟩

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