Branch Prediction is a widely used technique to optimize pipelined microprocessor architectures. In this paper, a High Level Synthesis (HLS) approach combining operation speculation and branch prediction is presented. In the proposed design flow, the CDFG (Control Data Flow Graph), is obtained by compiling the application. A speculation Graph is built. This graph allows to evaluate the potential of each branch to be predicted and the potential of each related Basic Block BB to be speculated. A target BB is then selected and scheduled using a list scheduling algorithm. A couple of BBs that will be predicted during the execution of the target BB is created. Operations of the couple are associated and speculativally scheduled in the target BB before being bounded to functional units. This step is repeated until all the BBs are scheduled. Finally, the RTL architecture is generated. The interest of branch prediction techniques in term of timing performances, and its impact on area are evaluated through first experiments.