Power-aware design of digital controller for step-down converter is discussed and compared to a standard analog counterpart so as to verify the feasibility in System-on-Chip. A tri-mode digital controller IC in 0.35 μm CMOS process is presented to demonstrate such a solution including a PID, a so-called quarter PID and a robust RST compensator. The compensators respectively address the steady-state, stand-by and transient modes according to the operating conditions of the step-down converter. An idle-tone free condition for the Σ - Δ DPWM is considered to reduce the inherent tone noise under DC-excitation while generating a quasi-pure modulation signal compared to a traditional approach. Experimental results verify closed-loop performances and lead to a power assessment model suggesting feasible applications.