In this paper, we present a nanometric layout generation tool for analogue building blocks called devices. We focus on the procedural routing methods inside devices. A device may have one or more folded transistors' fingers merged into at least one stack depending on the chosen layout style. We present two routing methods: intra-stack and inter-stack to ease the routing of the wired segments. Taking advantage of both routing methods, the layout generation tool provides a range of transistor folding to respect the designer-defined constraints (either electrical or physical). Both routing methods are used to generate different layout styles. The layout generation for a differential pair device is illustrated using four layout styles: interdigitated, mirror, 2D common-centroid and M2 modules. Keywords: Migration, Layout Generation, Routing, Stress effects