In order to address the large variety of channel coding options specified in existing and future digital communication standards, there is an increasing need for flexible solutions. Recently proposed flexible solutions in this context generally presents a significant area overhead and/or throughput reduction compared to dedicated implementations. This is particularly true while adopting an instruction-set programmable processors, including the recent trend toward the use of Application Specific Instruction-set Processors (ASIP). In this paper we illustrate how the application of adequate algorithmic and architecture level optimization techniques on an ASIP for turbo decoding can make it even an attractive and efficient solution in terms of area and throughput. The proposed architecture integrates two ASIP components supporting binary/duo-binary turbo codes and combines several optimization techniques regarding pipeline structure, trellis compression (Radix4), and memory organization. The logic synthesis results yield an overall area of 1.5mm 2 using 90nm CMOS technology. Payload throughputs of up to 115.5Mbps in both double binary Turbo codes (DBTC) and single binary (SBTC) are achievable at 520MHz. The demonstrated results constitute a promising trade-off solution between throughput and occupied area comparing with existing implementations.