Linear Space Boostrap Communication Scheme - Archive ouverte HAL
Pré-Publication, Document De Travail Année : 2012

Linear Space Boostrap Communication Scheme

Résumé

We consider a system of $n$ processes with ids not a priori known, that are drown from a large space, potentially unbounded. How can these $n$ processes communicate to solve a task? We show that $n$ a priori allocated Multi-Writer Multi-Reader (MWMR) registers are both needed and sufficient to solve any read-write wait-free solvable task. This contrasts with the existing possible solution borrowed from adaptive algorithms that require $\Theta(n^2)$ MWMR registers. To obtain these results, the paper shows how the processes can \emph{non-blocking} emulate a system of $n$ Single-Writer Multi-Reader (SWMR) registers on top of $n$ MWMR registers. It is impossible to do such an emulation with $n-1$ MWMR registers. Furthermore, we want to solve a sequence of tasks (potentially infinite) that are sequentially dependent (processes need the previous task's outputs in order to proceed to the next task). A non-blocking emulation might starve a processor forever. By doubling the space complexity, using $2n-1$ rather than just $n$ registers, processes can erase each other's write operation, just a bounded number of times, and consequently the computation is wait-free rather than non-blocking.
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Dates et versions

hal-00717235 , version 1 (16-07-2012)
hal-00717235 , version 2 (21-08-2012)

Identifiants

  • HAL Id : hal-00717235 , version 1

Citer

Carole Delporte-Gallet, Hugues Fauconnier, Eli Gafni, Sergio Rajsbaum. Linear Space Boostrap Communication Scheme. 2012. ⟨hal-00717235v1⟩
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