In the context of large versatile platform for embedded real time system on chip, a fine grained dynamically reconfigurable architecture (at a first approach an FPGA) can be used as one possible computational resource. In order to manage this resource in that kind of context we need an OS kernel able to manage such a resource. Both the history of micro-processor based system and our previous work based on currently available FPGA devices led us to think that not only an OS kernel must be defined to handle an FGDRA but a FGDRA must also be designed to handle this OS kernel. This article relate our original work in this direction. OLLAF\footnote{Operating system enabled Low LAtency Fgdra}, an original FGDRA core that we have designed and modelized using VHDL will be presented as well as a more general view of our approach of a FGDRA and its related OS kernel.