Bottom-up digital system-level reliability modeling - Archive ouverte HAL
Communication Dans Un Congrès Année : 2011

Bottom-up digital system-level reliability modeling

Résumé

We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.

Domaines

Micro et nanotechnologies/Microélectronique

Lucie Torella  : Connectez-vous pour contacter le contributeur

https://hal.science/hal-00651936

Soumis le : mercredi 14 décembre 2011-15:31:31

Dernière modification le : lundi 16 décembre 2024-15:38:04

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Dates et versions

hal-00651936 , version 1 (14-12-2011)

Identifiants

Citer

N.R. Amador, V. Huard, E. Pion, F. Cacho, D. Croain, et al.. Bottom-up digital system-level reliability modeling. Custom Integrated Circuits Conference (CICC'11), Sep 2011, San Jose, Ca., United States. pp.1 - 4, ⟨10.1109/CICC.2011.6055343⟩. ⟨hal-00651936⟩

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