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Communication Dans Un Congrès Année : 2011

Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor

Résumé

Soft errors have been emerged as an important reliability concern of modern ICs. In this work we have implemented an efficient error detection scheme in a low power DSP/MCU processor. Our scheme achieves high error detection efficiency at low hardware cost by means of an original combination of double-sampling and latch based-design into the so-called GRAAL architecture. The implementation of our design in 65nm and 45nm process nodes has confirmed the advantages of the GRAAL architecture: low area and power penalties and negligible performance degradation. Its high error detection efficiency was demonstrated by performing extensive simulations of single-event transients (SETs).
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Dates et versions

hal-00651920 , version 1 (14-12-2011)

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Citer

H. Yu, M. Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh. Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor. 16th IEEE European Test Symposium (ETS'11), May 2011, Trondheim, Norway. pp.93 - 98, ⟨10.1109/ETS.2011.20⟩. ⟨hal-00651920⟩

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