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Article Dans Une Revue Japanese Journal of Applied Physics Année : 2011

Patterning Strategy for Monoelectronic Device Platform in a Complementary Metal Oxide Semiconductor Technology

Résumé

We report a patterning strategy for building the first monoelectronic device complementary metal oxide semiconductor (CMOS)-compatible platform, including a single-electron transistor (SET) and multiple coupled quantum dots. Aggressive hybrid lithography (e-beam and deep UV are combined) and plasma etching are used to form adapted silicon active areas and gates, with a minimum size of 14 nm and a pitch of 80 nm after etching. These aggressive dimensions enable the study of double dots, a key structure for the more complex quantum circuits emerging now.
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Dates et versions

hal-00647505 , version 1 (02-12-2011)

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S. Pauliac-Vaujour, R. Wacquez, C. Vizioz, T. Chevolleau, M. Pierre, et al.. Patterning Strategy for Monoelectronic Device Platform in a Complementary Metal Oxide Semiconductor Technology. Japanese Journal of Applied Physics, 2011, 50 (6), pp.06GF15-06GF15-5. ⟨10.1143/JJAP.50.06GF15⟩. ⟨hal-00647505⟩
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