Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue IEEE Electron Device Letters Année : 2011

Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells

Matthieu Deloge
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Bruno Allard
Joël Damiens
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Elise Le-Roux
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Mustapha Rafik
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Résumé

The optimization of the programming voltage and the dimensions of antifuse bitcells is a design challenge due to antagonistic parameters. An optimization approach is presented using a time-dependent dielectric breakdown (TDDB) model. Fowler-Nordheim wear-out current and TBD power-law models are identified using electrical characterizations performed on antifuse bitcells fabricated in standard 40-nm CMOS. The TDDB model allows the calculation of the programming voltage according to a targeted TBD and the antifuse bitcell dimensions. As a result, it was shown that the lowest programming voltage is obtained for a small capacitor, whereas the size of the drift transistor has a second-order impact.
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Dates et versions

hal-00629363 , version 1 (05-10-2011)

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Matthieu Deloge, Bruno Allard, Philippe Candelier, Joël Damiens, Elise Le-Roux, et al.. Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells. IEEE Electron Device Letters, 2011, 32 (8), pp.1041 - 1043. ⟨10.1109/LED.2011.2158054⟩. ⟨hal-00629363⟩
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