An 8Gsps, 65nm CMOS Wideband Track-and-Hold
Résumé
A track-and-hold (T&H) circuit has been designed and fabricated using the 65nm CMOS technology from STMicroelectronics. A fully differential architecture has been adopted. The circuit exhibits a -3dB input bandwidth wider than 8GHz. At 8GHz, the maximum sampling frequency, the measured overall power consumption and gain are 178mW and 0dB, respectively. The T&H core dissipates around 40mW. The measured total harmonic distortion (THD) at Nyquist sampling conditions is about -37dB. The circuit die area is 1.1mm².