An 8Gsps, 65nm CMOS Wideband Track-and-Hold - Archive ouverte HAL
Communication Dans Un Congrès Année : 2011

An 8Gsps, 65nm CMOS Wideband Track-and-Hold

Résumé

A track-and-hold (T&H) circuit has been designed and fabricated using the 65nm CMOS technology from STMicroelectronics. A fully differential architecture has been adopted. The circuit exhibits a -3dB input bandwidth wider than 8GHz. At 8GHz, the maximum sampling frequency, the measured overall power consumption and gain are 178mW and 0dB, respectively. The T&H core dissipates around 40mW. The measured total harmonic distortion (THD) at Nyquist sampling conditions is about -37dB. The circuit die area is 1.1mm².

Domaines

Electronique
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Dates et versions

hal-00608608 , version 1 (13-07-2011)

Identifiants

  • HAL Id : hal-00608608 , version 1

Citer

Diego Rossoni Mattos, P. Hellmuth, Cyril Recoquillon, S. Gauffre, Ph. Cais, et al.. An 8Gsps, 65nm CMOS Wideband Track-and-Hold. 9th IEEE NEWCAS (2011), Jun 2011, BORDEAUX, France. pp.200-208. ⟨hal-00608608⟩
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