This work reports on the implementation of a 2.4 GHz ultra low power (ULP) low noise amplifier (LNA) in a standard CMOS 0.13 µm process. The proposed design methodology consists in optimizing the tradeoff between RF performances and current consumption of the MOS transistor. The supply of the circuit controlled by a 3bits DAC varies from 0.4 to 0.6 V. This digital tuning allows maximizing the figure of merit of the LNA. The approach yields the operating point within the sweet spot region of the amplifying transistors. Experimental results of the circuit indicate a power dissipation of 60 µW@0.4V, a noise figure of 5.3 dB, and a forward gain of 13.1 dB. The IIP3 and ICP1 are -12 dBm and -19 dBm, respectively. This works aims the development of a complete RF front end for micro-watt radio