Turbo product code decoder without interleaving resource: From parallelism exploration to high efficiency architecture - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue Journal of Signal Processing Systems Année : 2011

Turbo product code decoder without interleaving resource: From parallelism exploration to high efficiency architecture

Résumé

This article proposes to explore parallelism in Turbo-Product Code (TPC) decoding through a parallelism level classification and characterization. From this design space exploration, an innovative TPC decoder architecture without any interleaving resource is presented. This architecture includes a fully-parallel SISO decoder capable of processing n symbols in one clock period. Syntheses results show the better efficiency of such an architecture compared with existing solutions. Considering a six-iteration turbo decoder of a BCH(32,26)2 product code, synthesized in 90 nm CMOS technology, 10 Gb/s can be achieved with an area of 600 Kgates. Moreover, a second architecture enhancing parallelism rate is described. The throughput is 50 Gb/s while an area estimation gives 2.2 Mgates. Finally, comparisons with existing TPC decoders and existing LDPC decoders are performed. They validate the potential of proposed TPC decoder for Gb/s optical fiber transmission systems.

Domaines

Electronique
Fichier principal
Vignette du fichier
fulltext.pdf (940.1 Ko) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)
Loading...

Dates et versions

hal-00573278 , version 1 (03-03-2011)

Identifiants

  • HAL Id : hal-00573278 , version 1

Citer

Camille Leroux, Christophe Jego, Patrick Adde, Deepak Gupta, Michel Jezequel. Turbo product code decoder without interleaving resource: From parallelism exploration to high efficiency architecture. Journal of Signal Processing Systems, 2011, 64 (1), pp.17-29. ⟨hal-00573278⟩
395 Consultations
1035 Téléchargements

Partager

Gmail Facebook X LinkedIn More