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Chapitre D'ouvrage Année : 2010

Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case

Résumé

Self-timed rings are a promising approach for designing high-speed serial links or clock generators. This study focuses on the ring stage components – a C-element and an inverter - and compares the performances of different implementations of this component in terms of speed, power consumption and phase noise. We also proposed a new self-timed ring stage - only composed by a C-element with complementary outputs - which allows us to increase the maximum speed of 25% and reduce the power consumption of 60% at the maximum frequency. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics.
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Dates et versions

hal-00564558 , version 1 (09-02-2011)

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  • HAL Id : hal-00564558 , version 1

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O. Elissati, E. Yahya, Laurent Fesquet, S. Rieubon. Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Springer, pp.137-149, 2010, Lecture Notes in Computer Science, Vol. 6448. ⟨hal-00564558⟩

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