This paper presents the design and the measurement results of a novel Voltage Controlled Delay Line (VCDL) dedicated to an original architecture of Delay Locked Loop (DLL): the Factorial Delay Locked Loop (F-DLL). Based on the multiphase ring oscillator technique, the proposed VCDL offers, among others, two outputs in phase quadrature. These last ones allow the F-DLL to be zero-IF compliant and becomes a good candidate for multi-standard local oscillator. The proposed circuit has been fabricated in a 130nm CMOS-SOI technology from STMicroelectronics. Measurement results confirm the low quadrature phase error of the topology (inferior to 5°) and the ability of the F-DLL to synthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications, while offering very interesting performances in term of phase noise and settling time