This work deals with the study and the realization of Built-In Self-Tests (BIST) for LNAs and RF VCOs (Voltage-Controlled Oscillators). The increasing complexity of RF integrated circuits is creating an obstacle for the correct measurement of the main RF blocks of any transceiver. Some nodes are not accessible, the voltage excursion of the signals is getting lower and lower and high frequency signals cannot be driven off the die without a main degradation. The common test techniques become then very expensive and time consuming. The wafer sort is firstly approached. The proposed solution is the implementation of a BIST strategy able to discriminate between faulty and good circuits during the wafer test. The chosen methodology is the structural test (fault-oriented). A fault coverage campaign is carried out in order to find the quantity to monitor on-chip that maximizes the probability to find all possible physical defects in the CUT. Silicon demonstrators for wafer sort purposes are implemented using the ST CMOS 130nm and 65nm processes. They include an LNA, a current detector, a 3.5GHz VCO, an LDO, a temperature and supply-voltage independent voltage reference, a peak-to-peak voltage detector and comparators