Processor cache memory management deeply impacts performances and power consumption of electronic devices. As technology empowers to integrate more functionalities into these electronic chips, their design becomes more challenging. Computer-aided design softwares developed to generate chips are significantly faster but do not optimize power consumption. It is the reason why this work is concerned with the optimization of cache memory allocation. The problem addressed is called MemExplorer, it can be formulated as follows: for a given number of memory banks and an external memory, find the allocation of data structures so as to minimize loading time. MemExplorer is similar to the k-weighted graph coloring problem if banks are not subject to capacity constraints. A close problem is to determine the minimum number of memory banks with infinite capacity so as to have no open conflict, this turns out to be the classical graph coloring problem. As both problems are NP-hard we propose a VNS metaheuristics.