The Interest in synthesis of custom Digital Signal Processors (DSP) using automated design flow like High Level Synthesis greatly increased in the last years. This phenomenon is due to the growing processing complexity and the time to market constraint. Dedicated processor component design is a complex process, for which tools must optimize the datapath and its controller. In this paper, we propose a controller design flow based on mapping Finite-State Machines into Memory Blocks in order to limit the critical path delay in the controller. Our design flow approach takes into account DSP circuit singularities providing efficient area saving compared to other approaches (more than 18% up to 42% on real applications).