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Communication Dans Un Congrès Année : 2010

A memory Mapping Approach for Parallel Interleaver design with multiples read and write accesses

Cyrille Chavet
Philippe Coussy

Résumé

For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which always finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest our approach. This research was supported by the European project DAVINCI.
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Dates et versions

hal-00482682 , version 1 (27-05-2010)

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Cyrille Chavet, Philippe Coussy. A memory Mapping Approach for Parallel Interleaver design with multiples read and write accesses. IEEE International Symposium on Circuits and Systems (ISCAS), May 2010, Paris, France. page 3168-3171, ⟨10.1109/ISCAS.2010.5537955⟩. ⟨hal-00482682⟩
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