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Communication Dans Un Congrès Année : 2007

Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies

Résumé

In future nanotechnologies failure densities are predicted to be several orders of magnitude higher than in current CMOS technologies. For such failure densities existing fault tolerance implementations are inadequate. This work presents several principles of building multiple-fault tolerant memory cells and logic gates for circuits affected by high defect densities as well as a first evaluation of the area cost and performance.

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Dates et versions

hal-00472162 , version 1 (09-04-2010)

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Citer

Lorena Anghel, M. Nicolaidis. Defect Tolerant Logic Gates for Unreliable Future Nanotechnologies. International Conference on Artificial Neural Networks (IWANN), Jun 2007, San Sebastian, Spain. pp.422-429, ⟨10.1007/978-3-540-73007-1⟩. ⟨hal-00472162⟩

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