60 GHz cascode LNA with interstage matching: performance comparison between 130nm BiCMOS and 65nm CMOS-SOI technologies - Archive ouverte HAL Access content directly
Conference Papers Year : 2009

60 GHz cascode LNA with interstage matching: performance comparison between 130nm BiCMOS and 65nm CMOS-SOI technologies

Abstract

This paper presents a comparative study between two mm-wave technologies from STMicroelectronics: 130nm BiCMOS and 65nm CMOS-SOI, through the implementation of a single stage LNA at 60GHz. Both distributed and lumped design approaches are investigated to work out the best trade-off between silicon saving and performances. The two circuits achieve respectively 12dB and 6dB gain, 3.6dB and 4.5 dB noise figure under 2.5V and 1.2V supply voltage for BiCMOS9MW and CMOS-SOI technologies. The LNA are based on cascode topology with a specific interstage matching for ft and fmax improvement. The current density and transistor sizing are set to perform the lowest NF at 60GHz, the current consumption is 3.7mA and 13mA for BiCMOS9MW and CMOS-SOI LNA respectively.

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Electronics
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Dates and versions

hal-00418915 , version 1 (22-09-2009)

Identifiers

  • HAL Id : hal-00418915 , version 1

Cite

Cédric Majek, Raffaele Severino, Thierry Taris, Yann Deval, André Mariano, et al.. 60 GHz cascode LNA with interstage matching: performance comparison between 130nm BiCMOS and 65nm CMOS-SOI technologies. Signals, Circuits & Systems, Nov 2009, Jerba, Tunisia. pp.25-28. ⟨hal-00418915⟩
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