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Communication Dans Un Congrès Année : 2008

A flexible network-on-chip simulator for early design space exploration

Résumé

The communication requirements of large multi-core systems are convened by on-chip communication fabrics generally referred to as networks-on-chip (NoC). We have designed a simulation environment that allows early exploration of the performance and cost parameters of network-on-chip communication architectures, which is able to handle arbitrary topologies and routing schemes. The simulator implements a flit-level message-passing mechanism and supports application data specified as input trace files or generated at run-time by synthetic traffic generators.

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Dates et versions

hal-00417335 , version 1 (15-09-2009)

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Citer

C. Grecu, A. Ivanov, S. Saleh, C. Rusu, Lorena Anghel, et al.. A flexible network-on-chip simulator for early design space exploration. 1st Microsystems and Nanoelectronics Research Conference (MNRC 2008), Oct 2008, Ottawa, Canada. pp.33-36, ⟨10.1109/MNRC.2008.4683371⟩. ⟨hal-00417335⟩

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