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Communication Dans Un Congrès Année : 2009

Hardware Architecture for H.264/AVC INTRA 16X16 Frame Processing

Résumé

In this paper, we present an efficient H.264 / AVC Intra 16x16 Frame Coder System. The System achieves realtime performance for video conference applications. The INTRA 16X16 is composed by intra 16x16 prediction, integer transform, quantization AC, inverse integer ransform, inverse quantization AC, quantization DC, adamard, inverse quantization DC, and inverse integer ransform. The proposed hardware is implemented in HDL. The VHDL RTL code works at 160 MHz in an Altera tratix II FPGA and it code 129 Mpixels per second. This work will be used as an Intellectual Property (IP) integrated in H.264/AVC encoder.
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Dates et versions

hal-00405442 , version 1 (20-07-2009)

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Citer

Hassen Loukil, S. Arous, Ahmed Ben Atitallah, Patrice Kadionik, Nouri Masmoudi. Hardware Architecture for H.264/AVC INTRA 16X16 Frame Processing. DTIS: IEEE International Conference on Design & Technology of Integrated Systems in Nanoscal Era, Apr 2009, Cairo, Egypt. pp. 82-85, ⟨10.1109/DTIS.2009.4938029⟩. ⟨hal-00405442⟩
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