Hardware wrapper classification and requirements for on-chip interconnects.
Résumé
The new SoC paradigms brought on-chip interconnections in foreground. In order to achieve more reuse, flexibility, and performance, bus based interconnections are no more sufficient. The link between IP blocks and interconnections, the transport layer of the OSI reference model, enable a clean separation of computation and communication. As far as we know, no study has been yet performed on a customisable transport layer according to both interconnection and application. This paper propose some requirements that will have to be taken into account while designing hardware wrappers, and a classification of the services such a wrapper can implement.