Efficient on-chip communications for data-flow IPs
Résumé
We explain a systematic way of interfacing data-flow hardware accelerators (IP) for their integration in a system on chip. We abstract the communication behaviour of the data flow IP so as to provide basis for an interface generator. We also explain which parameter this interface generator has to take into account. We validate our interface mechanism by a cycle accurate bit accurate simulation of a SoC integrating a data-flow ip.
| Origine | Fichiers produits par l'(les) auteur(s) |
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