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Article Dans Une Revue IEEE Communications Letters Année : 2007

Simplified hardware bit correlator

Résumé

This letter proposes a suboptimal implementation of a binary correlator suitable for detecting a known fixed pattern in a binary stream. The theoretical performances in terms of the probability of nondetection and the probability of false alarm are evaluated. These performances show that the degradations are negligible. Compared to a proprietary core provided by FPGA vendor, this implementation allows a 15 % look-up table reduction, a 30 % register reduction and up to a 30 % higher clock frequency in a FPGA.

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Electronique
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Dates et versions

hal-00353876 , version 1 (16-01-2009)

Identifiants

  • HAL Id : hal-00353876 , version 1

Citer

Christophe Cunat, Emmanuel Boutillon. Simplified hardware bit correlator. IEEE Communications Letters, 2007, vol. 11 (n°6), pp.531-533. ⟨hal-00353876⟩

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